1. Field of the Invention
The present invention relates to a delay optimization designing system and a delay optimization designing method for a logic circuit and a control program, and more particularly to a delay optimization designing system and a delay optimization designing method for a sequential circuit and a control program.
2. Description of the Related Art
For delay optimization of a logic circuit, two methods are available including a delay optimization method for a sequential circuit which performs optimization regarding flip-flops and/or latches and another delay optimization method for a portion of a combinational circuit which exists between a flip-flop and a latch, between flip-flops and/or between latches. The present invention specifically relates to a method of delay optimization for a sequential circuit.
Conventionally, for delay optimization of a sequential circuit, a method called “retiming” is available and disclosed, for example, in Japanese Patent Laid-Open No. 290232/1994 (hereinafter referred to as document 1). This is a method for changing the position of a flip-flop to improve the worst delay.
Further, such a delay optimization method as described below is disclosed in Japanese Patent Laid-Open No. 2000-305962 (hereinafter referred to as document 2).
In this method, first, attention is paid to a specific flip-flop. Then, it is discriminated whether or not both of two conditions are satisfied including a first condition that the delay in a combinational circuit on the input side (preceding stage) of the flip-flop satisfies restrictions required in design with a predetermined margin and a second condition that the delay in a combinational circuit on the output side (succeeding stage) of the flip-flop does not satisfy restrictions required in design. Then, if both of the conditions are satisfied, then the flip-flop is substituted into a level-sensitive latch which immediately passes input data therethrough.
However, the method disclosed in the document 1 has such drawbacks as described below.
It is a first problem that, since the position of a flip-flop changes, operation of the flip-flop which makes a base of a logic analysis is different between an initial logic circuit and a logic circuit after optimization. Therefore, there is a drawback that, if a person who has designed the initial logic circuit tries to perform a logic analysis after optimization, then it is difficult for the person to take a suitable countermeasure.
It is a second drawback that, although the position of the flip-flop is changed, the delay of the overall logic circuit is not reduced.
On the other hand, in the method disclosed in the document 2, a flip-flop is substituted into a latch when, without depending upon whether or not the flip-flop has a delay margin, there is a delay margin on a combinational circuit in the preceding stage and there is no restriction violation of delay on a combinational circuit in the succeeding stage. Therefore, even if there is a flip-flop which itself has a delay margin thereon, the flip-flop is not substituted into a latch. As a result, sufficient delay optimization is not achieved.